Most every digital data-processing system includes a clock. Generated by an oscillator circuit, clocks emit electrical pulses which are used to synchronize almost every operation of the system. When taken together, these electrical pulses form a pulse train. In most cases, events within the individual timing dependent components of a data processing system must occur in a particular sequence.
A timing dependent component is any component that is required to be in step with the master clock pulse train to ensure proper operation of the computer system. A timing dependent component may be an individual digital circuit, a grouping of individual digital circuits, or any other clock dependent system entity. For example, the central processing unit (CPU) executes instructions, parts of instructions, and parts of parts of instructions in step with the pulse train that is emitted by a master system clock. Conventional data latches receive data, store data, and transfer it in response to different clock signals. On a larger scale, buses regulate the flow of data from one unit to another according to these clock signals. Storage registers must receive address and data signals in a predetermined order. Similarly, registers at different locations on a processor chip and on different chips must exchange sequential signals without overlap.
Simply stated, a computer system cannot function without a trustworthy master clock. Beyond being trustworthy, the performance of the computer system itself is directly dependent upon the speed at which a master clock operates. Since system performance (i.e., response time) is critical to the success of any given computer system, engineers are designing computer systems with faster and faster clocks. While super fast master clocks are desirable from a sales perspective, they present terrible internal control problems to computer system designers. As mentioned, proper function of timing dependent components requires that they are all in step with the master clock pulse train. However, beyond this requirement is the need to propagate internal control signals so as to harmonize the timing dependent components in a way that allows the computer system to operate.
Hence, proper operation of the computer system depends upon the ability to make internal control signals affect all of the timing dependent components at the same time. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This is called single cycle control. Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry. These timing dependent components are said to reside outside of the single cycle domain. Accordingly, as clock speeds continue to increase, the single cycle domain is shrinking.
One possible solution to this problem is to introduce delay into the control methodology so as to ensure that distant timing dependent components receive control signals at the same time as closer timing dependent components. However, the longer the delay period, the more uncertain delay becomes. If the delay is most likely two clock cycles, there may be a chance that in fast circuits the control signal will actually arrive in one cycle. If the delay is increased to ensure that it is impossible for control signals to arrive in one cycle, the control signal may in the end take three cycles to arrive. Such delays can be carefully adjusted during manufacturing, but this is extremely expensive. Further as circuits age, they often speed up or slow down. Hence, expensive reworking may be required.
Another solution to this problem is the use of expensive, high-speed technology which is itself fast enough to ensure that the control signal reaches the requisite components on time. However, this possible solution merely leaves the design engineer with a choice between a costly solution and no solution at all. Further, it is clear that even this expensive alternative will become unavailable as clock speeds become so fast that even the most costly solutions prove inadequate.